This invention relates to an input/output driver for a programmable logic device, and more particularly to an input/output driver capable of supporting a plurality of differential input/output standards.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output (xe2x80x9cI/Oxe2x80x9d) pins, with the connections of the pins to the interconnect structure also being programmable and being made through suitable I/O buffer circuitry.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor-transistor logic (xe2x80x9cTTLxe2x80x9d), in which a logical xe2x80x9chighxe2x80x9d signal was nominally at 5 volts, while a logical xe2x80x9clowxe2x80x9d signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signaling schemes, such as LVTTL (Low Voltage TTL, which exists in a 3.3-volt version or a 2.5-volt version), PCI (Peripheral Component Interface, which requires a 3.3-volt power supply), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants). Most recently, differential signaling schemes requiring two I/O pins have been developed. The first of these differential signaling schemes was LVDS (Low Voltage Differential Signaling). Other differential signaling schemes include BLVDS (Bus LVDS), LVECL (Low Voltage Emitter-Coupled Logic), LVPECL (Low Voltage Positive Emitter-Coupled Logic), CML (Current Mode Logic), and LDT (Lightning Data Transport). Other such schemes may be developed in the future.
While the various differential signaling schemes have in common the use of two I/O pins, they differ in common mode output voltage (Vos), differential output voltage (Vod), output current and output impedance. In particular, while the various standards allow some variability on the input side, each of these standards requires tight control on the output side.
In view of the foregoing it would be desirable to be able to provide a programmable logic device capable of supporting a plurality of different differential signaling schemes.
It is an object of the present invention to provide a programmable logic device capable of supporting a plurality of different differential signaling schemes. This and other objects of the invention are accomplished in accordance with the principles of one aspect of the invention by providing a programmable logic device having a pair of output terminals and a differential output driver for driving the pair of output terminals in accordance with a differential signaling scheme. A programmable current-limiting circuit is operatively connected to the differential output driver for selectably configuring the differential output driver for use with any one of a plurality of differential signaling schemes. By selectively limiting the current between a voltage source and the differential output driver and between the differential output driver and ground, the output impedance, as well as the common mode voltage and differential output voltage can be varied.
The PLD is programmable to allow any of the input and/or output buffers to which an I/O pin is connected to be used. This allows the PLD to provide differential signaling capabilities, if that is what is desired, without having to dedicate I/O pins to that particular type of use. Because a differential signaling connection requires a pair of I/O pins, while many other signaling protocols require only one I/O pin per connection, the PLD circuitry is programmable to allow I/O pins to be used in pairs for differential signaling or individually for other types of signaling.
To help make the speed of differential signaling circuitry more uniform across the operating voltage range permitted by the various differential signaling standards, circuitry is provided for strengthening at least one of the complementary current sources or sinks used in differential signaling input buffers when the operating voltage is such that the circuitry associated with the other current source or sink is no longer able to help the input buffer operate. The thus-strengthened current source or sink helps to maintain the speed of the input buffer even though the circuitry associated with the other current source or sink is no longer operating effectively. Hysteresis circuitry may be provided in differential signaling input buffers to help the buffer reject spurious input signal fluctuations. Pull-up connections may be provided on differential signaling input signal leads to help protect differential signaling input buffer from producing erroneous output signals in response to open or short-circuit conditions on those input signal leads.
A differential signaling output buffer in accordance with the invention is constructed to help keep the output voltages within a chosen differential signaling scheme standard or specification despite variations due to such factors as (1) manufacturing process inconsistencies, (2) temperature changes, and (3) power supply voltage fluctuations. The differential signaling output buffer includes differential output switching circuitry connected in series via resistors between power and ground potentials. One of the resistor circuits preferably includes a current source which tends to increase in resistance as the power supply potential increases, thereby helping to counteract the effect of increasing power supply voltage. The transistors in the differential output switching circuitry and the resistors in series with that circuitry are made so that they all have similar changes in resistance due to manufacturing process variations and temperature changes. This helps keep the differential signaling output voltages within the differential signaling scheme specifications despite these types of variations or changes. Capacitors are also preferably included in the differential signaling output buffer to improve the performance of the circuitry in relation to switching transients.
The programmable current limiting circuits referred to above, which preferably are positioned between the supply voltage and the differential output driver, and between the differential output driver and ground, preferably are networks of resistors or other impedance elements, each element of which can be bypassed by a controllable switch (e.g., a transistor or pass gate). It is straightforward then, to see how the output impedance and current can be controlled.
The current limiting circuits and the differential output driver also form a voltage divider. Controlling the voltage drops across the current limiting circuits thereby allows control of the voltage drop across the differential output driver (i.e., the differential output voltage) as well as the voltage drops between the supply and the differential output driver and between the differential output driver and ground (which determines the common mode voltage).